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Range Open System Architecture (ROSA) Engineering S
MIT/LL's ROSA I
Real-Time Open System Architecture (ROSA) was originally developed by the Massachusetts Institute of Technology (MIT) Lincoln Laboratory (LL) to standardize the hardware configuration and software structure of radar systems. The MIT/LL's ROSA started as the backend electronics of the Radar (hence the R in ROSA is sometimes referred to as Radar) but has since expanded to other instrumentation systems requiring Real-time response, including radar and optics. Before the ROSA project, the instrumentation radars at major test ranges are built with custom hardware using highly-specialized proprietary interfaces. The goal of the ROSA project is to design an open architecture using Commercially Off The Shelf (COTS) hardware with non-proprietory interfaces for radar systems. In addition to MIT’s Haystack Observatory, several variants of the ROSA design have been installed at the Reagan Test Site, Eastern Range, Western Range, Pacific Missile Range Facility, and other forward-deployed DoD assets.
A block diagram of the a variant of the MIT/LL's ROSA system is shown in Figure 1. Key features are as follows:
- All the subsystems are housed in a VME64X chassis with Motorola Single Board running VxWorks.
- The fileserver and display computers are Dell servers running Red Hat Linux Enterprise.
- The Main Radar Computer is hosted in an SGI server running IRIX.
- All the inter-communication is established with 1 Gigabit Ethernet network.
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We have highly trained engineers who received technology-transfer from MIT/LL on the development of the ROSA project since 2009. Our engineers have assisted in installing and testing several ROSA I systems at the Pacific Missile Range Facility. Our engineers developed numerous system updates/algorithms that are now incorporated in the current ROSA I baseline.
ROSA I with Linux MRC Block Diagram
MIT/LL's ROSA I with MRC upgrade
With the discontinuance of the Silicon Graphics Incorporated's (SGI) Origin server product line, the Main Radar Computer is re-hosted in a Dell Server running Red Hat Linux Enterprise operating system. To match the processing power of an SGI multi-compute node Origin server with 16 processors, the Dell server is populated with four sockets of multi-core processors. The radar Real-Time Processing (RTP) software is re-coded to execute from 64-bit MIPS RISC processor to Intel’s 64-bit Xeon processors.
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Our highly trained engineers have recently upgraded the architectural structure of a ROSA I with Linux MRC to meet cybersecurity compliance.
ROSA II Software Formation Block Diagram
MIT/LL's ROSA II
The Real-time Open System Architecture (ROSA) II is the latest iteration of the ROSA framework. ROSA II retained the basic hardware structure of ROSA I. The significant change is the structure and operation of the software. A block diagram of the software structure for the ROSA II is shown above. It is designed to improve the following features over ROSA I predecessor:
- Modularity: Each software functionality is transformed into individual standalone components and stored in a repository. Each component has well-defined input and output variables.
- Portability: Communication between software components is performed over the middleware, which removes its direct dependency on the operating system. This would allow for the software to be ported to any type of operating system. The middleware is Third-party software created by RTI.
- Scalability: Since the software functionality is divided into components, the features and capabilities can be easily added by the addition of components.
- Flexibility: Each software component in the new sensor repository can be updated without changing the source components.
The current ROSA II implementation is primarily employed on the radar Real-Time Programming software in the Main Radar Computer. With the restructuring of the software, the following were also performed:
- Most of the source code is re-coded into object-oriented C++
- The software is more net-centric with the incorporation of Web-service for component status reporting.
- Python scripts are used in the Graphical User Interface
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XonTech's WB-COSIP
The WideBand-COherent Signal Processing radar was developed by XonTech, Inc. in the 1990s. It has at least 20-ft Cassegrain antenna and 3-MW C-Band Klystron transmitter. The backend electronics includes the following:
- Four standard VME chassis for the Timing & Waveform Generator, Antenna Control Subsystem, Analog-to-Digital Converter, and Digital Signal Processors
- Two custom 19” chassis housing the Up/downconverters and receivers
- Two-cabinet transmitter housing the three-stage amplification of solid-state, Travelling Wave Tube, and klystron
- Numerous servers that run the Radar Real-Time programming, Transmit-controllers, Displays, and RAID recorders
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Our engineers upgraded the Timing & Waveform Generator, Analog-to-Digital Converter, and Digital Signal Processor chasses to address the obselences of parts. The Timing & Waveform Generator upgrade includes Phase IV Arbritrary Waveform generator. The ADC and DSP upgrade is based on Annapolis MicroSystems Wildstar boards.